Table of Contents
DreamCell CPU design [2016 .. ongoing]
Justification
Some abstractions are an unaffordable luxery
Waiting for technology that doesn't exist yet
- massive bandwidth
how to fill all blocks
- Articles
- One transistor SRAM ($.025μm2$) 2015
- Gate-all-around key to 5nm SRAM cell ($.0205μm2$) 2018
- Photonic crystals used to make optical RAM
- The Planar Tree Packing Theorem
Philosophy
- General purpose processor
- no specialized units.
- per clock reconfigurable regions vs. set and forget FPGA config.
- Scalable congruent regions, a 2x2 function block scales to the same configuration as a 4x4 function block. They perform the same function, only differing in the width of the input.
- Localized data into regions, like a patch space.
Von Neumann architecture doesn't scale.
Design
Simulating in JADE
Need to emulate a photonic bus. clone the current register device and set the cap to 0, risetime to 0. the bus will for an N*N cell there will be a N-wide bus for each row.
Simulating in C
- Instructions
So there's instruction configuration data, and inherent cell features, abilities. cells have 8'wire to NESW nbrs.
TODO: reword the following paragraph with real technical vocab. There are PROG cells, like DATA cells. PROG cells hold opcode data, which is instruction configuration data. So each cell has 256 different possible configurations. Some runs will require neighbor PROG cells to help with configuration to minimize chatter with the outboard photonics controller which needs to lock path segments from the edge of the chip to the target domain.
- UI
- Features
save design
Information bottleneck
The size of configuration data is lower bounded by. the more specific a computation gets, the more information is required to describe it. There should be a optimized middle ground for any given processing unit. Even compressed configuration data may
Argument configuring by heading
A cell has a heading, depending on heading. Like relative addressing in two dimensions with make configurations easier to visualize. A cell with heading North looks Left to find West. A cell with heading South looks Left and finds East. So, the cell can be rotated simply by changing the two heading bits. A change of heading changes the cell arguments. A cell with heading West may look LEFT at a SOUTH neighbor for argument 1 and looks R at a N nbr for arg 2. If that cell changes heading to N, then look L for arg1 at W, and R for arg2 at E.
| L | R | F | B | Heading | f(a,b) |
|---|---|---|---|---|---|
| a | b | North | f(L, R) | ||
| a | b | North | f(L, F) | ||
| a | b | North | f(L, B) | ||
| b | a | North | f(F, R) | ||
| b | a | North | f(B, R) | ||
| a | b | North | f(F, B) |
| L | R | F | B | Heading | f(a,b) |
|---|---|---|---|---|---|
| a | North | f(L) | |||
| a | North | f(R) | |||
| a | North | f(F) | |||
| a | North | f(B) |
#+ENDCENTER
Segment Broadcasting
A cell may broadcast an 8-bit value. The broadcast will occupy a 1, 2, 3 or 4 segments, each of which is to be terminated by a blocking cell.
Types of broadcasts
- Filled Broadcast: Every cell in the segment receives the value of the source broadcast cell.
- Portal Broadcast: Only the target portal cell receives the value from the source broadcast cell.
System Requirements
- A broadcast segment is a set of adjacent row or column of cells that act as repeaters.
- A broadcast starts from the broadcast cell and terminates at a blocking cell.
- Any cell can broadcast except bBLOCK.
- A broadcast segment delivers values quickly, the current model assumes a signal transmitted on a broadcast segment is driving a valid 8-bit value at each cell of a broadcast segment. For segments with many cells, this implies large capacitance and high rise/fall times. Therefore, photonics hardware may be needed to facilitate driving such signal in one cycle.
- bBLOCK cell config, for terminating broadcast segments, row/col partitioning.
Stalling evolution
Two approaches
Continue and repeat the operation (don't stall)
Instead of stalling after completing an operation, a source cell could set a flag that says: "I have a value ready in the data register!", and generate a \(\overline{\textrm{STALL}}\) signal and apply to target neighbor STALL pins.
Stop after one operation (stall immediately)
When a cell finishes running an operation, the cell may need to reserve the computed value for more than one cycle. In this case it should stall. So, there needs to be a stall bit and it needs to be written to at the right time.
Glossery
Source Cell (src)
A cell that acts as the source of a data value.
Target Cell (tgt)
A cell that receives data in some context where a source cell has been defined.